1. Technical Field
The present disclosure relates to an integrated memory circuit comprising a memory erasable and/or programmable electrically by means of a second voltage greater than the supply voltage.
The present disclosure also relates to a device for supplying an erase program high voltage to an integrated circuit.
2. Description of the Related Art
The integrated memory circuit market is currently experiencing a demand for programmable integrated circuits at very low prices, small sizes, and having a minimal number of interconnection terminals (contact pads). Such integrated circuits generally offer a limited memory size, sometimes only several tens or hundreds of bits. They may be reprogrammable by the user, or be programmed once and for all in the factory. The memory is generally of the electrically erasable and programmable (EEPROM) type.
Indeed, numerous applications exist for such integrated memory circuits, such as electronic tags containing a serial number programmed in the factory, calibration circuits with various components (sensors, light-emitting diodes LEDs, . . . ) containing calibration data programmed in the factory and possibly reprogrammable during use, etc.
To write data in their memories, such integrated circuits use an erase program voltage with a high value, conventionally between 10V and 15V, clearly larger than their supply voltage, which is on the order of 3V to 5V.
During the 1980's, this erase program high voltage was supplied to integrated circuits by means of a dedicated connection terminal. This connection terminal was later removed and replaced by an embedded charge pump capable of supplying the erase program voltage from the supply voltage of the integrated circuit. At this time however, it is no longer conceivable to return to the previous solution because the addition of such a connection terminal is contrary to the current specifications for a reduction of the number of integrated circuit connection terminals.
The architecture of a conventional integrated circuit of the type considered here is shown schematically in FIG. 1. The integrated circuit IC1 comprises an EEPROM type memory MEM1, a control circuit CCT1, a charge pump CP, a circuit PPCT, a ground terminal P0 (GND), a terminal P1 receiving a supply voltage Vdd, a connection terminal P2 to receive and/or emit a data or clock signal S1, and a connection terminal P3 to receive or emit a data or clock signal S2.
The control circuit CCT1 is configured to execute memory read or write commands received by the intermediary of terminals P2, P3. As an example, FIGS. 2A, 2B show the forms of the signals S1, S2 during the reception of a write command via a bus I2C. The signal S1 is in this case the data signal “SDA” (“Serial DAta”) provided by the protocol I2C and the signal S2 is the clock signal “SCL” (“Serial CLock”) provided by this protocol.
The command is received during a phase E1 by the intermediary of signal S1 that carries the bits at 1 and at 0. The circuit CCT1 then starts an erase phase E2 of a memory target zone designated by the command, then a program phase E3 of memory cells in the erased target zone. To this end, the circuit CCT1 activates the charge pump CP and the circuit PPCT. The charge pump CP supplies a high voltage HV to the circuit PPCT. This latter shapes this high voltage HV and supplies to the memory MEM1 an erase program high voltage Vpp with a regulated amplitude and a controlled duration, for example a voltage ramp followed by a voltage plateau with a value close to the voltage HV. The ramp-plateau signal may be supplied two times to the memory, first during the phase E1 and then during the phase E2.
The provision of an embedded charge pump however is detrimental in terms of cost price and of silicon surface area occupied by the integrated circuit. A charge pump includes several capacitors on the order of several Pico farads pF each, occupying a non-negligible silicon surface area. In addition, the regulation of the voltage HV by means of the circuit PPCT to obtain the voltage Vpp relies on a stable reference voltage and a specific circuitry that also occupies a non-negligible silicon surface area.
Thus, it may be desirable to simplify the structure of an integrated memory circuit using an erase program high voltage to write data in its memory.
Independently of this, it may also be desired to provide a device to supply an erase program high voltage to one or more integrated circuits.